TSMC reported Q1 2026 revenue of $35.9 billion — up 40.6% year-over-year and 6.4% sequentially — with net income of $18 billion, a 58% increase that marks the eighth consecutive quarter of double-digit profit growth. The headline numbers are notable. What they obscure is more significant: a 66.2% gross margin and 50.5% net profit margin in a capital-intensive manufacturing business running $52–56 billion in annual capex. Those margins are not the product of favorable demand alone. They are the signature of a structural moat that existing coverage has largely failed to name.
Why Manufacturing Margins at This Level Are Unusual
Semiconductor fabrication is capital destruction at scale under normal market conditions. Building and equipping a leading-edge fab costs $20–30 billion per facility. Customers demand continuous process improvements on fixed contract timelines. Yield losses at leading nodes routinely reach 30–50% during ramp. Under these conditions, gross margins in the 40–50% range are considered strong.
TSMC’s 66.2% gross margin is not in that range. For context, ASML — which sells the EUV lithography machines TSMC depends on and holds its own near-monopoly position — operates at roughly 50% gross margins. TSMC, which buys from ASML and runs the equipment at scale, is posting margins 16 points higher. The mechanism is pricing power derived from supply inelasticity: there is no alternative source for 3nm or 5nm wafers at production volume. Customers cannot negotiate on price without accepting queue risk on capacity, and queue risk translates directly into missed product cycles.
Node mix data from the Q1 report makes the concentration clear. Advanced nodes (3nm and 5nm combined) now account for 61% of wafer revenue — 25% from 3nm, 36% from 5nm. At these nodes, TSMC has no peer with production-scale capacity. Intel Foundry is still qualifying at 18A. Samsung’s 3nm yield figures remain below competitive parity by most analyst estimates. The pricing environment at the leading edge is, for practical purposes, uncontested.
CoWoS Capacity Expansion Signals Where the Next Constraint Lives
The margin story is not limited to the front-end wafer business. TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity has been the binding constraint on AI accelerator production since 2023. Q1 results confirm monthly CoWoS capacity has been raised to 125,000 wafers — a figure that represents significant expansion but still falls short of demand from customers building out large-scale GPU clusters.
TSMC is simultaneously targeting 165,000 monthly wafers of 3nm capacity. The combination of front-end node ramp and back-end packaging expansion defines the capital deployment rationale for running at the high end of the $52–56 billion 2026 capex range. In any other industrial context, $56 billion in annual capex on $35.9 billion in quarterly revenue would raise questions about return on invested capital. At 50.5% net margins, the math is self-evidently favorable.
The IDC projection that the Foundry 2.0 market will surpass $360 billion in 2026 — up 17% year-over-year — with TSMC’s market share expanding to 44%, provides the structural backdrop. TSMC is not merely growing with the market; it is growing market share within a market that is itself accelerating.
Q2 Guidance and Full-Year Forecast Remove Ambiguity About Demand Trajectory
TSMC guided Q2 2026 revenue to $39.0–40.2 billion, implying sequential growth of 8.6–12.0% on top of the Q1 beat. The full-year forecast of greater than 30% revenue growth — issued at a moment when the company has strong visibility into wafer start commitments — removes significant uncertainty about whether the AI infrastructure buildout will moderate in the near term.
CEO C.C. Wei described AI-related demand as “extremely robust,” language that, from a CEO who historically uses measured phrasing in investor calls, carries signal. The Q2 guidance range is also notably tight — a $1.2 billion spread on a $39+ billion quarter — suggesting TSMC has high confidence in near-term booking visibility.
The capex commitment to the high end of the $52–56 billion range is the more durable signal. Capex at this scale requires multi-year demand conviction; TSMC does not build capacity speculatively. The 2026 commitment extends capacity investment decisions that will take 18–24 months to reach production readiness, which means TSMC’s internal demand model already extends through 2027–2028 at levels that justify continued scale investment. For more on how advanced packaging supply constraints shape the broader AI infrastructure market, see our analysis of TSMC’s advanced packaging and the Nvidia supply chain.
What to Watch
- CoWoS allocation decisions: TSMC’s internal capacity allocation between major AI customers — Nvidia, AMD, Google, Amazon — will determine which hyperscalers can execute their infrastructure roadmaps on schedule in the second half of 2026. Watch for any commentary on allocation in the Q2 earnings call.
- 3nm yield and pricing at the N3E node: As 3nm ramps from 25% to a larger share of revenue, yield improvements will have an outsized impact on gross margin. Any margin expansion beyond 66.2% in Q2 or Q3 will confirm that 3nm economics are maturing ahead of schedule.
- Intel Foundry 18A qualification status: If Intel’s 18A node demonstrates production-quality yields by year-end 2026, it introduces the first credible alternative for a narrow class of leading-edge designs. The timeline for this matters to TSMC’s pricing power thesis.
- Arizona and Japan fab ramp timelines: TSMC’s geopolitical capacity distribution affects both subsidy realization and customer diversification. Delays in U.S. fab ramp affect both TSMC’s cost structure and U.S. government expectations about domestic semiconductor capacity. Related: our analysis of Section 232 semiconductor tariffs and their impact on AI infrastructure planning.
This article was produced with AI assistance and reviewed by the editorial team.
