RISC-V in 2026: AI, Automotive, and China Drive Adoption

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Key Claim: RISC-V’s 2026 momentum is not a story of Arm displacement — it is an open architecture that has identified three specific market conditions where it wins, and is executing with production silicon against each of them.

RISC-V has crossed a meaningful threshold. More than 13 billion cores built on the open instruction set architecture (ISA) have shipped to date, server-grade silicon from Alibaba and Ventana entered production in 2025, and automotive chip giants Bosch, Infineon, NXP, and Qualcomm have formally committed to standardising on it. Yet Arm still powers more than 95% of smartphones and holds commanding share in servers. The honest picture of RISC-V in 2026 is not a story of Arm’s displacement — it is a story of an open architecture that has identified three specific conditions under which it wins, and is executing against them.

What Changed: RVA23 and the Fragmentation Problem

For most of RISC-V’s history, its openness was also its weakness. Because any implementer could choose which extensions to include, two RISC-V chips were not guaranteed to run the same software stack. The October 2024 ratification of the RVA23 profile changed that calculus. RVA23 mandates hypervisor extensions, a standardised vector instruction set, and a minimum capability baseline that gives OS vendors a fixed target. Early RVA23-compliant silicon from Ventana and Alibaba’s C930 is the first test of that guarantee in production.

AI Accelerators: The Greenfield Advantage

The most commercially credible RISC-V traction in 2026 is in AI inference and training silicon, precisely because this market does not carry the software legacy that protects x86 and Arm in general-purpose computing. As explored in our analysis of custom silicon strategies at major hyperscalers, royalty-free open architectures are increasingly attractive at scale.

Ventana Micro’s Veyron V2 began shipping to hyperscaler and HPC customers in 2025 — making it the furthest along of the new RISC-V data-centre platforms. SiFive’s Intelligence X100 Gen 2 delivers 64 TFLOPS of FP8 performance at 2GHz, with first silicon expected in Q2 2026.

A longer-term signal came from NVIDIA. In July 2025, NVIDIA VP Frans Sijstermans announced that NVIDIA is working to bring CUDA support to RISC-V host processors. This is still early-stage: development runs on SiFive’s HiFive Premier P550 dev board, with no release timeline announced. If it reaches production, CUDA on RISC-V would break the assumption that CUDA-based AI systems require x86 or Arm host CPUs.

Automotive: The Strongest Deployment Signal

Mobileye reportedly began mass production of the EyeQ Ultra SoC in 2025. The chip contains 12 dual-threaded RISC-V cores and delivers up to 176 TOPS, targeting Level 4 autonomous driving.

More structurally significant is Quintauris, the Munich-based joint venture formed by Bosch, Infineon, NXP, Nordic Semiconductor, and Qualcomm. On 12 January 2026, Quintauris announced a partnership with SiFive to standardise high-performance RISC-V IP across next-generation zonal controllers and ADAS. Separately, Infineon announced it will extend its AURIX automotive MCU brand with a new RISC-V family.

These are not experimental partnerships. Bosch, Infineon, and NXP are foundational suppliers of automotive electronics at global scale. Their collective commitment to RISC-V standardisation means RISC-V IP will be embedded in component roadmaps that Tier 1 suppliers and OEMs design against for the next decade.

China: The Geopolitical Driver

US export controls have progressively restricted China’s access to advanced semiconductor manufacturing equipment. Arm Holdings is subject to US re-export restrictions that limit what Chinese companies can license. The RISC-V ISA, by contrast, is governed by RISC-V International — a Swiss non-profit — and is not controlled by any single US entity. No US export licence is required to implement a RISC-V core.

On 28 February 2025, Alibaba’s T-Head unit announced the XuanTie C930 — a 64-bit, superscalar, out-of-order server CPU built on RISC-V, scoring above 15 points/GHz on SPECint2006 benchmarks. In January 2026, Zhejiang Province published targets for domestic production of 7–3nm chips and fifth-generation RISC-V architecture. According to CSIS analysis, China’s domestic semiconductor self-supply rate grew from 25% to 35% between 2024 and 2025. This supply chain dimension connects directly to the pressures we covered in our AI semiconductor supply chain analysis.

Where Arm Is Not Threatened

Arm powers over 95% of smartphone SoCs. The entire mobile software ecosystem — Android, iOS, third-party app stores — is compiled against Arm. Arm Neoverse is gaining significant share in data-centre workloads. RISC-V server silicon from Ventana and Alibaba is production-shipping, but at the early-adopter stage.

Arm’s durability in premium markets is not primarily about microarchitecture. It is about the toolchain, the profilers, the certified compilers, the ISV software packages, and the support contracts that exist for Arm and not yet for RISC-V. On that dimension, Arm’s lead is substantial and will narrow slowly.

Implications / What to Watch

CUDA on RISC-V reaching a release candidate will materially change the ROI calculation for building AI inference servers on RISC-V. Quintauris silicon in production zonal controllers will be the first instance of RISC-V in safety-critical automotive infrastructure at OEM scale. China’s RISC-V ecosystem maturity — the C930’s compatibility with RVA23 means Chinese RISC-V designs are on a converging standards path with the Western ecosystem.

RISC-V is not displacing Arm. It is occupying the spaces where Arm’s licensing model, or geopolitical exposure, or software incumbency does not apply. Those spaces are growing.

This article was produced with AI assistance and reviewed by the editorial team.